Memory Management

Memory Management Techniques

Techniques allowing memory to be shared among multiple processes:

Overlays – The memory should contain only those instructions and data that are required at a given time.
Swapping – In multiprogramming, the instructions that have used the time slice are swapped out from the memory.
Single Partition Allocation – The memory is divided into two parts. One part is kept to be used by the OS and the other is kept to be used by the users.
Multiple Partition Schemes – Fixed Partition (divided into fixed size) and Variable Partition (divided into variable sized).
Allocation Schemes: First Fit (allotted first hole that fits), Best Fit (allotted hole that fits best, leaving minimum memory empty), Worst Fit (allotted hole that leaves maximum gap).

Advanced memory management strategies:

Paging – The physical memory is divided into equal sized frames. The main memory is divided into fixed size pages. The size of a physical memory frame is equal to the size of a virtual memory frame.
Segmentation – Segmentation is implemented to give users a view of memory. The logical address space is a collection of segments.
Page Fault: Raised by hardware when a running program accesses a memory page that is mapped into the virtual address space, but not loaded in physical memory.

Algorithms used to decide which page to replace when a page fault occurs:

First In First Out (FIFO) – Simplest algorithm. Operating system keeps track of all pages in the memory in a queue, oldest page in front. Belady’s anomaly: possible to have more page faults when increasing the number of page frames.
Optimal Page replacement – Pages are replaced which are not used for the longest duration of time in the future. Perfect but not possible in practice.
Least Recently Used (LRU) – The page will be replaced with the one which is least recently used.

Hardware components to speed up memory access:

Cache Memory: An extremely fast memory type that acts as a buffer between RAM and the CPU. It holds frequently requested data and instructions so that they are immediately available to the CPU when needed.
TLB (Translation Lookaside Buffer): A memory cache that is used to reduce the time taken to access a user memory location. It is a part of the chip’s memory-management unit (MMU).